1. Field of the Invention
The present invention relates to a semiconductor device having a test mode and a normal mode as operating modes, and more specifically, to a semiconductor device that employs a higher input level in the test mode than in the normal mode.
2. Description of the Background Art
In some cases, a semiconductor device such as a dynamic random access memory (DRAM) and the like has a super VIH level applied at a terminal in order to set the semiconductor device to a test mode. The super VIH level is a high potential level that is greater than the logic high or H level that is employed when the operating mode is the normal mode. For instance, in the semiconductor device which utilizes a power-supply voltage of 3.3V, the super VIH level would be about 5V. When the super VIH level is applied to a prescribed input terminal, the semiconductor device is set to the test mode.
The reason for purposely applying the super VIH level to a terminal to set the device to the test mode is that there is the fear of a user erroneously setting the device to the test mode if a simple command input alone is required to set the test mode.
By performing the detection of the super VIH level, the test mode would never be readily entered into as long as the user complies with the conditions of the input voltage so that the stable operation in the normal mode would be achieved.
FIG. 10 is a schematic diagram related to the description of an arrangement for detecting the super VIH level of a conventional double data rate synchronous dynamic random access memory (DDR SDRAM).
Referring to FIG. 10, a terminal T1 to which a bank address signal BA1 is supplied is connected to an address buffer 4a by an interconnection line W1. Interconnection line W1 has a parasitic resistance R1 and a parasitic capacitance C1. Interconnection line W1 is connected to a control circuit 508 by an international line W2. Interconnection line W2 has a parasitic resistance R2 and a parasitic capacitance C2.
Control circuit 508 includes an SVIH detection circuit 22 for detecting that a super VIH level is supplied to terminal T1, and a test mode circuit 24 activated according to an output from SVIH detection circuit 22 for outputting test signals TE0 to TEk according to combinations of internal address signals INTA0 to INTAn.
When the potential supplied to terminal T1 is 3.3V or below, for instance, SVIH detection circuit 22 does not recognize the input voltage as the super VIH level. Thus, during the normal operation, an input signal supplied to terminal T1 is only used as bank address signal BA1. Bank address signal BA1 is input to address buffer 4a. Address buffer 4a outputs an internal address signal INTBA1. Internal address signal INTBA1 is used for the designation of a memory bank along with an internal address signal INTBA0 supplied via another terminal.
On the other hand, when the potential supplied to terminal T1 is 5V or greater, for instance, SVIH detection circuit 22 recognizes the input potential to be the super VIH level. In this case, SVIH detection circuit 22 activates test mode circuit 24. Test mode circuit 24 outputs test signals TE0 to TEk according to combinations of internal address signals INTA0 to INTAn. A variety of tests are designated by test signals TE0 to TEk, and a circuit provided with an activated test signal attains the state in which a prescribed test operation is possible. One example of the prescribed test operation is a power supply-related test.
As higher speeds of semiconductor devices are achieved, the restriction of the capacitance that is parasitic on a terminal becomes strict. When the parasitic capacitance of the terminal is great, the transmission of an input signal becomes slow. In addition, a higher drivability would be required of a device which outputs a signal in order to drive the terminal, which results in the increase in noise and in power consumption.
In a DDR SDRAM, for instance, an input capacitance of an address input terminal is required to be about 2 pF to 3 pF. The parasitic capacitance of the terminal results from a parasitic capacitance of an interconnection line connected to the terminal, capacitances of a gate, a drain, and a source of a transistor, and so on. As shown in FIG. 10, parasitic capacitances C1, C2 are added to terminal T1 to which bank address BA1 is input. In order to achieve a high speed operation, parasitic capacitance C2 should be made as small as possible. In order to prevent parasitic capacitance C2 from becoming large, an interconnection line has to be 2 mm or shorter, for instance. Thus, there is the restriction that SVIH detection circuit 22 must be disposed in the vicinity of an input pad.
Moreover, as opposed to terminal T1, other input terminals, such as a terminal to which bank address BA0 is to be input, for instance, do not have interconnection lines corresponding to interconnection line W2 connected to them, so that their parasitic capacitances would become C1. Consequently, problems arise in that the parasitic capacitances would differ according to the terminals and that the timing of signal input to an internal circuit would differ. In addition, an output terminal may be set to a disable state so as to allow the recognition of the super VIH level; however, there is a possibility of an output signal being delayed if an unnecessary additional capacitance is added to the output terminal.